High data rate dynamic rule processor for live network packet analysis


This project is proposing a flexible parser using live configuration parameters to specify processed incoming packets.
The associated git repository includes the sources of the packet parser architecture and the test probe.

Project requirements and tools

The global provided example project is built with Vivado 2016.4.
The integration is done on the NetFPGA SUME board.
The NetFPGA project is required to generate the project.

Associated paper


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