Ouessant HowTos: Quickstart

This page is still a Work in Progress. Feel free to signal any mistake/lack in the description.

First simulation

Here are the required steps to set a Ouessant based system up. For now, only Leon based platforms are possible


In order to use Ouessant, a few tools are needed.

The Ouessant code base and build architecture relies on GNU/Linux common building tools. We do not support Windows as a development platform. On a Debian/Ubuntu GNU/Linux distribution, you can get the required tools with the following command:

sudo apt-get install build-essential gcc make git bison flex 

Ouessant is a hardware design, thus CAD tools are needed according to your needs:

  • if you want to work in simulation, ModelSim is required.
  • if you want to work with Xilinx FPGA, ISE toolsuite with a valid license for the board you are using is required. Please note that for Nexys4 and Atlys board, ISE WebPack is sufficient. You will also need tools to program the board (impact for Xilinx, Adept for Digilent boards).
  • for Zynq based device, we use Vivado toolsuite

Furthermore, you will need the tools for the processor you are working with. For LEON based SoC, this means :

  • the compiler(s) for the SPARC processor (Linux or/and bare (​http://www.gaisler.com/index.php/downloads/compilers?task=view&id=161) according to your needs)
  • the GRMON debugger (​http://www.gaisler.com/index.php/downloads/debug-tools?task=view&id=190)

For Zynq (ARM based) SoC, this means: * the compiler(s) for the ARM processor (we use the compiler suite from Xilinx)

We assume that all those tools are available, and correctly configured. Please refer to the corresponding manuals if you need more information. Boards specific instruction for supported devices are provided in [OuessantBoards|the Ouessant boards page].

Getting started: setting up Ouessant environment

  1. Download the project repository:
    git clone https://redmine.telecom-bretagne.eu/git/ouessant/ 
  1. Go to the project's root (ie. the folder you have just created by cloning the repository). If you put it in your home directory, you can do this by typing :
    cd ~/ouessant
  2. Set up the Ouessant environment:
    make env-complete

    This will generate the complete environment for Zynq and Leon based systems.
    You can use
    make env-zynq
    make env-leon
    if you only want a single system.
    Warning : make sure that you have all the required permissions on the ouessant folder.

We provide as much automation as possible to speed up the process of getting a Ouessant processor up and running. You can get all available commands and help by typing make help in the command line.

The code is divided in 6 main directories (other directories will be described later):

  • ocp contains the main VHDL code for Ouessant,
  • data contains various data for Ouessant. In particular, it contains Coprocessor descriptions
  • drivers has all the example codes in it, for Linux and baremetal
  • socs is the main directory for complete example System on Chips
  • scripts contains tools for automation
  • tools is created to store tools for Ouessant, mainly the assembler

When you run the make env command, you download all required tools (especially the Leon tools), generate the Ouessant configurations, and compile the tools. You are now ready to compile a complete SoC with associated software, and run your first test.

Simulate a first Leon design

We are now going to simulate a Spiral FFT design using Ouessant.

  1. Go to the leon3-ouessant-mst-minimal folder by typing:
    cd socs/leon3-ouessant-mst-minimal/

    and compile the project by running
    make vsim

    By default, this will compile a Leon processor with required peripherals, and a Ouessant with a Spiral DFT (256 points) accelerator. Further information on how to change this design are given in the "Going further" section.
  2. The design is now compiled, we can compile the associated code. This is done by running
     make install 

    which will compile the code and create the RAM image for the design.
  3. Finally, type
    make vsim-launch

    to launch the simulation. This will launch ModelSim with the compiled design.
    You can then launch the simulation. We provide a complete wave configuration to show what is going on inside Ouessant. Type
     do wave.do
     run 30 ms

    to start the simulation. The device starts to do things around 1.6 ms. You should see the first result output around 2 ms, and the first values around 4.7 ms. This takes a few minutes to reach depending on your machine. While simulation is useful to debug the coprocessor, complete simulation of a Leon-based device can be long. If you see a result in the transcript, functional verification is faster (as long as it is working!) on the FPGA.

Going further

Going further: modifying the project

Congratulations, you launched your first Ouessant project!

You can now modify it if you want to suit your need. Here, we provide a description of what can be found where.

The SoC you are working on is based on the minimal Leon example from Gaisler. Nearly all the automation comes from Aeroflex. If you need to change things, two files can be useful:

  • leon3mp.vhd is the top-level file. You can find a ouessant0 instantiation. The orac generic of this instantiation defines which available accelerator you want to use. This is very basic, but will be improved in the next release of Ouessant. You can find valid values in @data/grlib-interface/devices.vhd" . Only a few are available for now, but you can add your own if you like.
  • Makefile is used to build the design. One specific variable is important here: PROGDIR. It is the path of the required program. You can change it as you like.

The code which is executed is typically stored in drivers/racs_examples/. In our case, we use the fft_float_test app, which runs a simple FFT test. The fft.S file is the Ouessant microcode. It is compiled and available in the fft_ouessant.[ch] files. You can change this in the Makefile. The main.c is the main code. It allocates data, initializes Ouessant, and runs infinitely the tests. You can comment in or out the 4 configuration macros:

  • SOFTWARE_VERSION allows usage of FFTW to compare the results
  • RANDOM_INPUT will randomly change inputs at each iteration
  • PRINT_RESULT will provide some info on the standard output
  • SIMULATE is defined to provide a ligher test code when simulating the design.

If you want to run a FPGA test, we advise you to define the first three macros.

Getting started: run Ouessant on a FPGA with Leon

For now, Ouessant is available on Atlys and Nexys4 boards, only with a Leon project. We describe how to run a test on Nexys 4 in the following steps. Atlys works the same, except that you do not use the same base designs.

Please note that due to a temporary bug, ethernet is currently not optional. This will be corrected in the next days

  1. First, we are going to generate the programming file for the FPGA. Change to the directory for the SoC you want to use, in our case:
     cd socs/leon3-ouessant-digilent-nexys4 
  2. If you need to change the project, do it now. Ouessant ships with a functional FFT design for Nexys 4.
  3. Build the design for FPGA:
     make ise 

    This will take around 30 minutes, once again depending on your machine (tests have been performed on an Intel Core i5 running at 2.8 Ghz, with 8 GB of RAM, and a SSD disk).
  4. Connect the FPGA board to your computer and turn it on. You need to connect:
    • the serial port and programming port (they are the same for Nexys4, so only one cable is required)
    • (optional) the ethernet port to an ethernet port of your host computer. This is not necessary, but recommended, since sending the example code can be very long otherwise. For baremetal testing, serial port is sufficient, loading will take a few seconds.
  5. Program the FPGA:
     make ise-prog-fpga
  6. Modify the code as explained in the previous part, and compile the software code:
     make install 
  7. (optional) If you use Ethernet, please ensure that the IP address is set on the network interface. It should be in the subnet.
  8. Connect to the loaded Leon design using one of the following:
    • if you want to use the serial port. Note that /dev/ttyUSB1 must be change to match the actual port
      grmon -uart /dev/ttyUSB1 -baud 38400 -u 
    • (optional) if you want to use Ethernet
      grmon -eth
  1. Load the compiled code in the Leon RAM by typing in the grmon command line interface:
    load systest.exe
  2. (optional) If you use Ethernet, connect a serial monitor to the board (Putty is a wonderful tool for this) using the correct parameters (baudrate is 38400).
  3. Run the test and check the results!

Getting started: run Ouessant on a FPGA with Zynq on ZedBoard

Working with Zynq is much more straightforward, since it doesn't require as much Third Party tools.
  1. Change into the correct directory
    cd socs/zynq-ouessant-zedboard
  2. Clean any previously generated files
    make clean
  3. Build for a given configuration
    make build
  4. Connect the ZedBoard and program the FPGA
    make prog-fpga
Once the hardware part is ready, we can proceed with the software part. We describe here how to run the Zynq examples.
  1. Change into the sofware Board Support Package directory
    cd drivers/zynq_examples/bsp
  2. Build the bsp library
  3. Change to the example code for your Ouessant CoProcessor. Here, we run the fft example.
    cd ../units/fft 
  4. Build the code
  5. Connect your ZedBoard to your computer and configure the serial port (on Linux, /dev/ttyACM0 with speed 115200)
  6. Launch xmd
  7. In XMD, configure the processor:
    source launch.tcl
  8. Run the app!

Have fun !