Gestion de projets

08/04/2015

22:56 Ouessant Révision c2dff177 (ouessant): Adding APB enabled IDCT

Adding interface between slave port (apb2coproc) and its testbench (basic validation only)
Adding top level (untested...

14/03/2015

19:28 Ouessant Révision d094271b (ouessant): Merge branch 'master' of frekilabs.fr:~git/ouessant

19:23 Ouessant Révision 14dc3bf5 (ouessant): Uplooading all last week developpment

Adding tops for ouessant in slv mode, and connected to apb, with correct simulation.
Adding full interface mst/slv ip...

08/03/2015

16:47 Ouessant Révision e88b905e (ouessant): Merge branch 'master' of frekilabs.fr:~git/ouessant

Conflicts:
Coprocessor/testbench/tb_coproc_slv_port.vhd
Coprocessor/vhd/dependency/COMMON_pkg.vhd

16:42 Ouessant Révision 6a389cda (ouessant): Adding slave only oouessant coprocessor

Creating generic memory
Creating interface block between system bus and coprocessor interface
Adding a few WIP files ...

06/03/2015

10:25 Ouessant Révision b8cb1d62 (ouessant): Merge branch 'master' of frekilabs.fr:~git/ouessant

10:24 Ouessant Révision 9b4c49cb (ouessant): Adding new version of slave interface to debug Erwan

01/03/2015

03:09 Ouessant Révision cc8e9266 (ouessant): Starting report for projet

7 pages written, no images, to be completed

25/02/2015

14:53 Ouessant Révision 043c8bdc (ouessant): Correcting a bug with testbench with slv

Adding bank and base_address port to communicate base addr to master interface

12:42 Ouessant Révision 7566bb4f (ouessant): Interface upload

Setting start on a pulse instead on continuous 1
Adding interface to give bank base address to master interface
Integ...