Philip-Dylan GLEONEC
Activity
Reported issues: 0
04/08/2015
- 10:56 PM Ouessant Revision c2dff177 (ouessant): Adding APB enabled IDCT
- Adding interface between slave port (apb2coproc) and its testbench (basic validation only)
Adding top level (untested...
03/14/2015
- 07:28 PM Ouessant Revision d094271b (ouessant): Merge branch 'master' of frekilabs.fr:~git/ouessant
- 07:23 PM Ouessant Revision 14dc3bf5 (ouessant): Uplooading all last week developpment
- Adding tops for ouessant in slv mode, and connected to apb, with correct simulation.
Adding full interface mst/slv ip...
03/08/2015
- 04:47 PM Ouessant Revision e88b905e (ouessant): Merge branch 'master' of frekilabs.fr:~git/ouessant
- Conflicts:
Coprocessor/testbench/tb_coproc_slv_port.vhd
Coprocessor/vhd/dependency/COMMON_pkg.vhd - 04:42 PM Ouessant Revision 6a389cda (ouessant): Adding slave only oouessant coprocessor
- Creating generic memory
Creating interface block between system bus and coprocessor interface
Adding a few WIP files ...
03/06/2015
- 10:25 AM Ouessant Revision b8cb1d62 (ouessant): Merge branch 'master' of frekilabs.fr:~git/ouessant
- 10:24 AM Ouessant Revision 9b4c49cb (ouessant): Adding new version of slave interface to debug Erwan
03/01/2015
- 03:09 AM Ouessant Revision cc8e9266 (ouessant): Starting report for projet
- 7 pages written, no images, to be completed
02/25/2015
- 02:53 PM Ouessant Revision 043c8bdc (ouessant): Correcting a bug with testbench with slv
- Adding bank and base_address port to communicate base addr to master interface
- 12:42 PM Ouessant Revision 7566bb4f (ouessant): Interface upload
- Setting start on a pulse instead on continuous 1
Adding interface to give bank base address to master interface
Integ...
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